WHQL Test Specification References: Chapter 4: PCI Test Specification
B188.8.131.52 Pass WHQL tests
Windows XP: Search for “PCI” to identify system-specific and device-specific topics in the HCT documentation.
B184.108.40.206 SEE B220.127.116.11
B2.5.4 PCI Controllers/Devices - Windows Experience
Design Guideline References: PC 2001 System Design Guide, Chapter 6, "Buses and Interfaces"
Hardware Design Guide 3.0 for Windows 2000 Server, Chapter 2
B18.104.22.168 Power management supported as defined in PCI Bus Power Management Interface Specification, Rev. 1.1 (PCI-PM)
System provides 3.3 V to all PCI connectors. [PCI-0123; SDG3:33)
System supports 3.3 Vaux if a system supports S3 or S4 states for integrated devices that support waking the system and all PCI slots including MiniPCI. [PCI-0131; SDG3:51; see FAQ B22.214.171.124 and B126.96.36.199]
PCI add-on cards that use 3.3 Vaux operate correctly, using a method such as the one described in Section 7.4.4 of PCI-PM 1.1. [PCI-0130.2]
Bus power states are correctly implemented. [PCI-0130; SDG3:50]
Local area network (LAN) and modem devices support wake-up per PCI-PM 1.1. [PCI-0132; SDG3:89]
See FAQ B2.5.5.
See also "PCI Power Management and Device Drivers" at http://www.microsoft.com/hwdev/desinit/pcipm.htm.
B188.8.131.52 Mini PCI devices support PCI 2.2, PCI-PM 1.1, and Mini PCI 1.0 specifications, and all other Logo requirements for PCI devices
"Compatibility Testing for Hot-Plugging Support for PCI Devices" at http://www.microsoft.com/hwdev/pci/hotplugpci.htm.
"Hot-Plug PCI and Windows Operating Systems" at http://www.microsoft.com/hwdev/pci/hotplugpci.htm.
B184.108.40.206 BIOS does not configure I/O systems to share PCI interrupts when APIC is activated
When an I/O APIC is enabled in the platform, the BIOS must configure the I/O systems such that non-PCI interrupts are not shared with PCI interrupts. At least four of the separate interrupt inputs in the I/O APIC must be dedicated to support PCI interrupts. The system layout and BIOS must minimize sharing of the PCI interrupts.
Mobile PC Note: In mobile systems, the BIOS can configure the I/O system to share PCI interrupts.
B220.127.116.11 DAC requirement [Clarification ]
Requirements for PCI adapters to support the PCI DAC command are defined in A1.1.6. See "Large Memory Enabled Device Driver Hardware and Software Requirements" in the Windows DDK. Design guidelines are summarized at http://www.microsoft.com/hwdev/newPC/PAEdrv.htm.
B18.104.22.168 AMR/MR PCI IDs [Clarification]
AMR devices and MR devices on the system board are not exempt from the requirement for SID and SVID.
May 28, 1999
B22.214.171.124 Control Method for PCI IDs [Logo Program Clarification]
[PCI-0126; SDG3:30, 31]
PC 99 System Design Guide erroneously cited _PS0 as the control method to use. However, _PS0 moves a device from Dx to D0. (The parent PCI bus is at issue in this case; thus, it is actually Bx to B0.) The problem is that a bus must be powered on before it can be assigned a bus number. Therefore, _PS0 must be run before a bus number is guaranteed to exist. However, if power hasn’t been cut to the bus, or if the bus has not been reset, there will be a bus number remaining from before the bus was placed in the Bx state. This is why _PS0 seems to work in some systems. _REG runs immediately after Windows assigns the bus number and immediately before the PCI driver scans the bus for children. That is what makes _REG the appropriate vehicle for making the children coherent.
After the operating system has control of the system, the SVID and SID registers must not be directly writable—that is, implementations that write these registers before the operating system takes control must disable writing to the SVID and SID registers after the registers have been set and before Windows assumes control of the system. For details, see http://www.microsoft.com/hwdev/devdes/pciids.htm.
FAQ Date: August 26,1999
B126.96.36.199 PCI-PM 1.1 and PME# [Logo Program Clarification9]
[PCI-0130; PCI-0131; SDG3:50]
Device requirements: PCI Bus Power Management Interface Specification, Revision 1.1 or later, is the only industry specification that ensures compatibility with the power management capabilities of Windows XP/Windows 2000, which uses PME# as the wake-up signal.
FAQ Date: May 6, 1999; December 22, 1999
Bus and bridge requirements: Requirements for supporting PCI-PM 1.1 and for correctly supporting 3.3 Vaux are defined at B2.5.4.
B188.8.131.52 3.3 Vaux power requirement [Clarification]
See the clarification on the PCI specification, "9.18 - 3.3 Vaux power delivery/consumption requirements FAQ," published by the PCI Special Interest Group (PCI SIG) at http://developer.intel.com/technology/iapc/pc99vqa.htm.
FAQ Date: March 19, 1999