B2.4 Parallel/Serial Devices

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B2.4 Parallel/Serial Devices

All general requirements in B1.0 are included by reference.

B2.4.1 Parallel/Serial Devices - Windows Compatibility

B2.4.1.1 Windows XP/Windows 2000: "Serial Port Devices" and Parallel Port Devices” in the Windows DDK

Windows 98/Me: “Virtual Communications Device Drivers” in the Windows Me DDK.
B2.4.1.2 Windows compatibility and implementation notes (general)

B2.4.1.3 Windows XP/Windows 2000: Enumerating Serial Devices in Windows 2000

B2.4.1.4 Windows 98/Me: VCOMM Port Driver Power Management Interface


B2.4.2 Parallel/Serial Devices - Industry Standards

B2.4.2.1 Standard Signaling Method for a Bi-directional Parallel Peripheral Interface for Personal Computers (IEEE 1284 specification)

Global Engineering Documents at http://global.ihs.com/

B2.4.3 Parallel/Serial Devices - Quality

WHQL Test Specification References:
Chapter 1: Introduction to HCT Test Specifications
B2.4.3.1 Pass WHQL tests

See B1.3.

Windows XP: See the “Motherboard” topic in the HCT documentation.

B2.4.4 Parallel/Serial Devices - Windows Experience

Design Guideline References:
Legacy Plug and Play Guidelines
B2.4.4.1 Plug and Play capabilities and operating system compatibility

Implemented as defined in Legacy Plug and Play Guidelines

Note: The following summarizes these legacy requirements, based on Legacy Plug and Play Guidelines:

  • Serial port meets device class specifications for its bus.

  • Legacy serial port is implemented as 16550A UART or equivalent and supports 115.2K baud.

  • Legacy serial port supports dynamic resource configuration.

  • Conflict resolution for legacy serial port ensures availability of at least one serial port.

  • Parallel port meets device class specifications for its bus.

  • Flexible resource configuration supported for each parallel port.

  • EPP support does not use restricted I/O addresses.

  • Compatibility, nibble mode, and extended capabilities port (ECP) protocols meet IEEE 1284-1994 specifications.

  • Port connectors meet IEEE 1284-I specifications, at minimum.

  • IEEE 1284 peripherals have Plug and Play device IDs.

  • Device identification string provides a Compatible ID key.

  • Daisy-chained parallel port device is Plug and Play capable.

B2.4.5 Parallel/Serial Devices - FAQs

See http://www.microsoft.com/winlogo/hardware/comm/.

B2.4.R Parallel/Serial Devices - Future Requirements

Announcement of additional future requirements will be published at http://www.microsoft.com/winlogo/hardware/comm/.

B2.5 PCI Controllers and Devices

All general requirements in B1.0 are included by reference.

B2.5.1 PCI Controllers/Devices - Windows Compatibility

B2.5.1.1 Driver device class support in related DDKs

Bus driver support is built in to Windows; see device class-specific entries in the Windows DDK and Windows Me DDK.
B2.5.1.2 Windows compatibility and implementation notes (general)

B2.5.1.3 PCI Device Subsystem IDs and Windows

B2.5.1.4 Compatibility Testing for Hot-Plugging Support for PCI Devices

B2.5.1.5 PCI Subsystem IDs and PCI-to-PCI bridge devices

B2.5.1.6 Windows XP/Windows 2000 PCI support

PCI IRQ Routing on a Multiprocessor ACPI System at http://www.microsoft.com/hwdev/onnow/ACPI-MP.htm
B2.5.1.7 Correct PCI implementations

[PCI-012x; SDG3:4x]

  • Device IDs include PCI Subsystem IDs. [PCI-0126; SDG3:45; see also FAQs A1.5.13, B2.5.5.3, B2.5.5.4]

  • System does not contain ghost devices. [PCI-0123; SDG3:36]

  • System uses standard method to close base address register (BAR) windows on nonsubtractive decode PCI bridges. [PCI-0124; SDG3:38]

  • Bus master privileges are supported for all connectors. [PCI-0123; SDG3:42]

  • Functions in a multifunction PCI device do not share writable PCI Configuration Space bit. [PCI-0123; SDG3:43]

  • PCI devices complete memory write transaction within specified times. [PCI-0125; SDG3:49]

  • Configuration Space is correctly populated. [PCI-0126; SDG3:44]

  • Interrupt routing is supported using ACPI. [PCI-0127; SDG3:46]

  • PCI-to-PCI bridges comply with PCI to PCI Bridge Specification 1.1. [PCI-0124; SDG3:37]

See "Configuring PCI-PCI Bridges on Windows 2000 and Windows XP" at http://www.microsoft.com/hwdev/pci/.

  • Adapters address full physical address space on a 64-bit platform; 32-bit PCI adapters used on the primary data path support the PCI DAC command, with the exception of 10/100 Ethernet devices.

See "Large Memory Enabled Device Driver Hardware and Software Requirements" in the Windows DDK. Design guidelines are summarized at http://www.microsoft.com/hwdev/newPC/PAEdrv.htm
[see FAQ B2.5.5.2]

  • Bus designs implement all bus requirements on expansion card connectors. [PCI-0123]

  • PCI devices decode only resources found in the Devices BAR. [SDG3:40]

B2.5.2 PCI Controllers/Devices - Industry Standards

B2.5.2.1 PCI Bus Power Management Interface Specification, Revision 1.1 or later

[PCI-0130; SDG3:37; see also FAQ B2.5.5.5]
B2.5.2.2 PCI Bus Power Management Interface Specification for PCI-to-CardBus Bridges

[PCCard-19; SYS-0024]

Note: Support of the CSTSCHG interrupt line is required only for devices that support wakeup events as defined in the PC Card standard.

Provided in Volume 11, PC Card Standard, Release 7, http://www.pcmcia.org/bookstore.htm.

B2.5.2.3 PCI Local Bus Specification, Revision 2.2 (PCI 2.2) or later

[PCI-0123; SDG3:33]
B2.5.2.4 PCI to PCI Bridge Specification, Revision 1.1

[PCI-0124; SDG3:37]
B2.5.2.5 PCI-X Specification, Revision 1.0

B2.5.2.6 Mini PCI Specification, Revision 1.0

B2.5.2.7 PCI Hot-Plug Specification, Revision 1.0


B2.5.3 PCI Controllers/Devices - Quality

WHQL Test Specification References:
Chapter 4: PCI Test Specification
B2.5.3.1 Pass WHQL tests

See B1.3.

Windows XP: Search for “PCI” to identify system-specific and device-specific topics in the HCT documentation.
B2.5.3.2 SEE B2.5.1.7

B2.5.4 PCI Controllers/Devices - Windows Experience

Design Guideline References:
PC 2001 System Design Guide, Chapter 6, "Buses and Interfaces"
Hardware Design Guide 3.0 for Windows 2000 Server, Chapter 2
B2.5.4.1 Power management supported as defined in PCI Bus Power Management Interface Specification, Rev. 1.1 (PCI-PM)

[PCI-0123; SDG3:28]

  • System provides 3.3 V to all PCI connectors. [PCI-0123; SDG3:33)

System supports 3.3 Vaux if a system supports S3 or S4 states for integrated devices that support waking the system and all PCI slots including MiniPCI. [PCI-0131; SDG3:51; see FAQ B2.5.5.5 and B2.5.5.6]

  • PCI add-on cards that use 3.3 Vaux operate correctly, using a method such as the one described in Section 7.4.4 of PCI-PM 1.1. [PCI-0130.2]

  • Bus power states are correctly implemented. [PCI-0130; SDG3:50]

  • Local area network (LAN) and modem devices support wake-up per PCI-PM 1.1. [PCI-0132; SDG3:89]

See FAQ B2.5.5.
See also "PCI Power Management and Device Drivers" at http://www.microsoft.com/hwdev/desinit/pcipm.htm.
B2.5.4.2 DELETED
B2.5.4.3 Mini PCI devices support PCI 2.2, PCI-PM 1.1, and Mini PCI 1.0 specifications, and all other Logo requirements for PCI devices
B2.5.4.4 Hot-Plug PCI supported via compatible driver solutions or ACPI


"Compatibility Testing for Hot-Plugging Support for PCI Devices" at http://www.microsoft.com/hwdev/pci/hotplugpci.htm.

"Hot-Plug PCI and Windows Operating Systems" at http://www.microsoft.com/hwdev/pci/hotplugpci.htm.

B2.5.4.5 BIOS does not configure I/O systems to share PCI interrupts when APIC is activated


When an I/O APIC is enabled in the platform, the BIOS must configure the I/O systems such that non-PCI interrupts are not shared with PCI interrupts. At least four of the separate interrupt inputs in the I/O APIC must be dedicated to support PCI interrupts. The system layout and BIOS must minimize sharing of the PCI interrupts.

Mobile PC Note: In mobile systems, the BIOS can configure the I/O system to share PCI interrupts.

B2.5.5 PCI Controllers/Devices - FAQs

B2.5.5.1 Current PCI-related FAQs

See http://www.microsoft.com/winlogo/hardware/pci/.
B2.5.5.2 DAC requirement [Clarification ]


Requirements for PCI adapters to support the PCI DAC command are defined in A1.1.6. See "Large Memory Enabled Device Driver Hardware and Software Requirements" in the Windows DDK. Design guidelines are summarized at http://www.microsoft.com/hwdev/newPC/PAEdrv.htm.

B2.5.5.3 AMR/MR PCI IDs [Clarification]


AMR devices and MR devices on the system board are not exempt from the requirement for SID and SVID.

May 28, 1999
B2.5.5.4 Control Method for PCI IDs [Logo Program Clarification]

[PCI-0126; SDG3:30, 31]

PC 99 System Design Guide erroneously cited _PS0 as the control method to use. However, _PS0 moves a device from Dx to D0. (The parent PCI bus is at issue in this case; thus, it is actually Bx to B0.) The problem is that a bus must be powered on before it can be assigned a bus number. Therefore, _PS0 must be run before a bus number is guaranteed to exist. However, if power hasn’t been cut to the bus, or if the bus has not been reset, there will be a bus number remaining from before the bus was placed in the Bx state. This is why _PS0 seems to work in some systems. _REG runs immediately after Windows assigns the bus number and immediately before the PCI driver scans the bus for children. That is what makes _REG the appropriate vehicle for making the children coherent.

After the operating system has control of the system, the SVID and SID registers must not be directly writable—that is, implementations that write these registers before the operating system takes control must disable writing to the SVID and SID registers after the registers have been set and before Windows assumes control of the system. For details, see http://www.microsoft.com/hwdev/devdes/pciids.htm.

FAQ Date: August 26,1999
B2.5.5.5 PCI-PM 1.1 and PME# [Logo Program Clarification9]

[PCI-0130; PCI-0131; SDG3:50]

  • Device requirements: PCI Bus Power Management Interface Specification, Revision 1.1 or later, is the only industry specification that ensures compatibility with the power management capabilities of Windows XP/Windows 2000, which uses PME# as the wake-up signal.
    FAQ Date: May 6, 1999; December 22, 1999

  • Bus and bridge requirements: Requirements for supporting PCI-PM 1.1 and for correctly supporting 3.3 Vaux are defined at B2.5.4.
B2.5.5.6 3.3 Vaux power requirement [Clarification]

See the clarification on the PCI specification, "9.18 - 3.3 Vaux power delivery/consumption requirements FAQ," published by the PCI Special Interest Group (PCI SIG) at http://developer.intel.com/technology/iapc/pc99vqa.htm.
FAQ Date: March 19, 1999

B2.5.R PCI Controllers/Devices - Future Requirements

Announcement of additional future requirements will be published at http://www.microsoft.com/winlogo/hardware/pci/.

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B2.4 Parallel/Serial Devices

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