• Table 6 – PAP vs. RAP across multiple buses.
  • Peak Advertised Performance




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    Peak Advertised Performance

    Real Application Performance




    Memory bus

    1,600 MBps

    975 MBps read

    550 MBps write

    327 MBps copy


    PCI bus

    133 MBps

    98.5 MBps

    SCSI bus (Ultra160)

    160 MBps

    98.5 MBps @ 1 MB read req.

    83.6 MBps @ 64KB read req.

    50 MBps write


    3ware 3W-5400

    Greater than 55MBps

    58.9 MBps @ 64KB read

    40 MBps write




    3Ware 3W-6800*

    (Alpha test unit)



    100+ MBps

    101 MBps @ 256KB read

    85 MBps @ 256KB write



    Hard disk

    (Atlas 10K)



    18MBps to 26MBps

    17 MBps to 24 MBps

    Hard disk

    (Fireball lct08)



    Up to 32 MBps

    12.4 MBps to 19 MBps



    Table 6 – PAP vs. RAP across multiple buses. The SCSI bus’s throughput was hampered by the adapter’s PCI bus interface, as the Ultra160 SCSI’s advertised PAP is higher than that of the PCI bus. The first generation 3ware card, despite being able to interface with four drives, has a limited throughput of 58.9MBps, or approximately the combined throughput of three of our Fireball IDE drives reading sequentially. However, in each of these cases, the half-power point was achieved.



      1. Symmetric Multiprocessing (SMP)

    All of our tests were run on a dual processor system. We found SMP had little effect on our throughput measurements. Since the measurements are already IO bound, increasing the number of processor cycles available does little to improve performance. We tested the single CPU case by booting Win2K using /NUMPROC=1 as an argument. This causes Win2K to function in a uniprocessor mode, ignoring the second processor. Overhead increased slightly when two CPUs were used as there was now some additional overhead incurred by synchronization code. In addition, Windows 2000 only allows one outstanding deferred procedure call (DPC) per SCSI adapter. We only had one adapter. For each of these reasons, we weren’t able to take advantage of the additional parallelism offered by the additional processor.




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