This section presents requirements for Windows NT–compatible IDE hardware, including adapters, peripherals, and any device that uses an IDE controller.
129 System includes IDE host controller and peripherals
It is not advised that IDE disks be present in a server, and ISA-based IDE is not allowed for servers. If IDE is implemented in a system, the IDE host controller and peripheral must meet all related requirements for devices and drivers, and they must meet the requirements defined in this section.
130 Controller complies with ATA 2 specification
Recommended: ATA 3 compliance.
All IDE adapters (and peripherals) must meet the hardware and software design requirements listed in the current version of the AT Attachment 2 specification.
131 Dual IDE adapters use single FIFO with asynchronous access or dual FIFOs and channels
PCI dual IDE adapters must be designed so that either channel can be used at any time; that is, the operating system does not have to serialize access between the primary and secondary channel at any time. Therefore, either the two channels are totally independent or a hardware arbitrator protects anything shared such as a PIO read pre-fetch buffer.
A design implementing a single FIFO that uses a hardware solution to synchronize access to both channels meets this requirement if the design does not require that a request on one channel be completed before another can be started.
IDE-based systems must be tested with IDE DMA enabled, and the system must not have an embedded single-FIFO dual-channel IDE controller.
Section 5.0 of the Compaq, Intel, Phoenix BIOS Boot Specification defines the implementation for dual asynchronous channels.
Dual-channel controllers that require special software to serialize channel I/O for a single prefetch FIFO do not meet these requirements. Such designs require serial access to one of four devices, defeating the primary advantage of asynchronous dual-channel controllers. Furthermore, such devices are non-standard and require custom driver support.
The introduction of non-standard IDE hardware is strongly discouraged because it negatively impacts traditional compatibility of the IDE interface. Notice, however, that dual-channel controllers which do not require special software to serialize channel I/O do meet these requirements.
132 System BIOS and devices support LBA
To enable support for IDE disk drives that are larger than 528 MB, the system BIOS must use a logical block addressing (LBA) scheme that is compatible with the BIOS/CMOS and IDE register set constraints. The system BIOS must also be able to enable and disable block mode and must be able to disable 32‑bit mode.
Although ATAPI was defined to be transparent to the BIOS, the BIOS must recognize the presence of ATAPI devices using the signature defined in SFF 8020i. In some cases, without such support, the BIOS might fail to configure the adapter if it does not see a device.
133 Controller and peripherals support PCI IDE bus mastering
The programming register set for PCI IDE bus master DMA is defined in SFF 8038i. IDE drives must comply with SFF 8038i to ensure fully featured hardware and Windows-compatible device driver support.
With ATAPI CD‑ROM, programmed I/O (PIO) demands placed on the system CPU can have a negative impact on performance and application processing, especially for multimedia. Bus master DMA IDE adapters, which leverage local bus data rates, can provide higher data rates and the ability to offload the system CPU from I/O transfers.
Other factors that encourage the adoption of bus master DMA include the increased disk media transfer rates, plus demands made by multitasking operating systems and multichannel/multidevice IDE configurations.
An exemption exists for ISA‑based, IDE-connected CD‑ROM devices that are used solely for the purpose of software installation on a server system. Such devices cannot be used for any other purpose, including access to data by client systems.
See also the following related requirement “IDE/ATAPI controller and devices support Ultra DMA/33” in this section.
134 IDE/ATAPI controller and devices support Ultra DMA/33
Ultra DMA/33 is required to avoid the bottleneck created by the current 16.6 Mb/s limit on disk transfer. Ultra DMA/33 also provides error checking for improved robustness over previous IDE implementations. This requirement applies to all IDE/ATAPI controllers and devices.
PCI chip sets must implement DMA as defined in SFF 8020i and must implement Ultra DMA/33 as defined in the specification submitted by Quantum Corporation for inclusion in the ATA 4 specification (proposed as ATA 4 1153 DR11).
An exemption exists for ISA-based, IDE-connected CD‑ROM devices that are used solely for the purpose of software installation on a server system. Such devices cannot be used for any other purpose, including access to data by client systems.
135 Controller and peripheral connections include Pin 1 cable designation with keyed and shrouded connectors
Pin 1 orientation must be designated by one edge of the ribbon cable and also on the keyed connector of the IDE or ATAPI controller and peripheral device. Designation of the keyed connector must be clearly indicated on or near the connector.
136 Peripherals comply with SFF 8020i, Version 2.5 or higher
This specification defines standard hardware and software design guidelines for ATAPI devices. See also the “Device supports Int 13h Extensions in system and option ROMs” requirement earlier in this chapter.
137 BIOS enumeration of all ATAPI devices complies with SFF 8020i, Version 2.5 or higher
ATAPI specification SFF 8020i, Version 2.5 or higher, defines the enumeration process for all ATAPI devices.
138 Devices support ATAPI RESET command
This item ensures that the ATAPI RESET command is processed by the peripheral, even if the firmware state cannot be determined. The controller should be reset by going into a power-on state (requests cleared, signature present), except leave any non-default mode values in their current state and leave the DRV bit unchanged. For more information, see Section 6.2 of SFF 8020i, Version 2.5 or higher.
139 Operating system recognizes the boot drive in a multiple-drive system
The implementation of boot-drive determination in multiple-drive systems is defined in Section 5.0 of the Compaq, Intel, Phoenix BIOS Boot Specification. This is the format that Windows NT uses for determining the boot drive as new bootable devices are introduced for servers. The system designer can use an equivalent method for boot-drive determination, but the method must ensure that the boot drive is recognized by the Windows NT operating system.
140 ISA address ranges 3F7h and 377h are not claimed by IDE controllers
Although IDE controllers might use these addresses, 3F7h and 377h also contain registers used by the FDC. To prevent resource conflicts, these addresses must not be claimed as device-register resources.
141 Device supports ATA STANDBY command
The IDE drive must implement the ATA STANDBY command according to the ATA standard to ensure that the drives are able to spin up properly after a STANDBY command. This command is defined in the ATA‑2 specification and in SFF 8020i.
It is recommended that the hard disk drive spin up and be able to complete a Read operation within 6 seconds of applying power and within 5 seconds of leaving ATA STANDBY mode and transitioning to ATA ACTIVE, as specified in the Storage Device Class Power Management Reference Specification, Version 1.0 or higher.
142 IDE hard drive is SMART-compliant and uses SMART IOCTL API
Self-Monitoring, Analysis, and Reporting Technology system (SMART) is an industry term used to describe technology to monitor and predict device performance.
The SMART IOCTL API Specification, Version 1.1 or higher, published by Compaq Computer Corporation and Microsoft Corporation, describes the API used by an application to issue SMART commands to an IDE drive under Windows NT Server.
For all server systems, IDE hard drives must be SMART-compliant.
| 