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APPLICATIONS OF MULTICORE DSPs
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| bet | 9/14 | | Sana | 23.07.2024 | | Hajmi | 0,76 Mb. | | #268329 |
Bog'liq TrendsInMulticoreDSP.GathererAPPLICATIONS OF MULTICORE DSPs
MULTICORE FOR MOBILE APPLICATION PROCESSORS
The earliest SoC multicore in the embedded space was the two- core heterogeneous DSP1ARM combination introduced by TI in 1997. These have evolved into the complex OMAP line of SoC for handset applications. Note that the latest in the OMAP line has both multicore ARM (symmetric multiprocessing) and DSP (for
heterogeneous multiprocessing). The choice and number of cores is based on the best solution for the problem at hand and many combinations are possible. The OMAP line of processors is optimized for portable multimedia applications. The ARM cores tend to be used for control, user interac- tion, and protocol processing, whereas the DSPs tend to be signal processing slaves to the ARMs, performing compute intensive tasks such as video codecs. Both CPUs have associated hardware accelerators to help them with these tasks and a wide array of specialized peripherals allows glueless con- nectivity to other devices.
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This multicore is an integration play to reduce cost and power in the wireless handset. Each core had its own unique function and the amount of interaction between the cores was limited. However, the development of a communications bridge between the cores and a master/ slave programming paradigm were impor- tant developments that allowed this model of processing to become the most highly used multicore in the embedded space today [37].
MULTICORE FOR CORE NETWORK TRANSCODING
The next integration play was in the transcoding space. In this space, the master/slave approach is again taken, with a
FOR PROGRAMMERS TO FEEL CONFIDENT ABOUT THEIR CODE, TIMING BEHAVIOR SHOULD BE PREDICTABLE AND REPEATABLE.
fallout of the tech bubble burst. They suffered from a lack of production quality tooling and no clear programming model. In general, they came in two types; arrays of arithmetic logic
host processor, usually servicing multiple DSPs, that is in charge of load balancing many tasks onto the multicore DSP. Each task is independent of the others (except for sharing pro- gram and some static tables) and can run on a single DSP CPU. Figure 10 shows the Agere SP2603, a multicore device used in transcoding applications.
Therefore, the challenge in this type of multicore SoC is not in the partitioning of a program into multiple threads or the coordination of processing between CPUs, but in the coor- dination of CPUs in the access of shared, non CPU, resources, such as DDR memory, Ethernet ports, shared L2 on chip mem- ory, bus resources, and so on. Heterogeneous variants also exist with an ARM on-chip to control the array of DSP cores.
Such multicore chips have reduced the power per channel and cost per channel by an order of magnitude over the last decade.
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