The next integration play was in the transcoding space. In this space, the master/slave approach is again taken, with a
FOR PROGRAMMERS TO FEEL CONFIDENT ABOUT THEIR CODE, TIMING BEHAVIOR SHOULD BE PREDICTABLE AND REPEATABLE.
fallout of the tech bubble burst. They suffered from a lack of production quality tooling and no clear programming model. In general, they came in two types;
arrays of arithmetic logic
host processor, usually servicing multiple DSPs, that is in charge of load balancing many tasks onto the multicore DSP. Each task is independent of the others (except for sharing pro- gram and some static tables) and can run on a single DSP CPU. Figure 10 shows the Agere SP2603, a multicore device used in transcoding applications.
Therefore, the challenge in this type of multicore SoC is not in the partitioning of a program into multiple threads or the coordination
of processing between CPUs, but in the coor- dination of CPUs in the access of shared, non CPU, resources,
such as DDR memory, Ethernet ports, shared L2 on chip mem- ory,
bus resources, and so on. Heterogeneous variants also exist with an ARM on-chip to control the array of DSP cores.
Such multicore chips have reduced the power per channel and cost per channel by an order of magnitude over the last decade.
