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Analog Dialogue 33-8 (1999)Bog'liq analog-to-digital-converter-architectures-and-choices1
10
100
1,000
10,000
FLASH
C = 2
n
–1
t = 1
PIPELINE
C
P
ⴛ
2
n/P
t = P
FLASH
16 BIT
12
10
5
BIT
8
12 BIT
16 BIT
SAR
C = 1
t
n
SUCCESSIVE
APPROXIMATION
1 BIT
1
5
10
15
DECISION CYCLES – t
NUMBER OF COMPARATORS – C
8
10
16
12
10
Figure 1. Tradeoff between decision cycles and comparators.
FLASH CONVERTERS
Conceptually, the
flash
architecture (illustrated in Figure 2) is quite
straightforward: a set of 2
n
–1 comparators is used to directly
measure an analog signal to a resolution of
n
bits. For a 4-bit flash
ADC, the analog input is fed into 15 comparators , each of which
is biased to compare the input to a discrete transition value. These
values are spaced one least-significant bit (LSB = FS/2
n
) apart.
The comparator outputs simultaneously present 2
n
–1 discrete
digital output states. If for example the input is just above 1/4 of
full scale, all comparators biased to less than 1/4 full scale will
output a digital “1,” and the others will output a digital “0.”
Together, these outputs can be read much like a liquid
thermometer. The final step is to level-decode the result into
binary form.
2
n
– 1(FULL SCALE)
.
.
.
A
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