Analog Dialogue 33-8 (1999)




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analog-to-digital-converter-architectures-and-choices

ADC
⌺
–
+
DIGITAL
A
SAMPLE
AND HOLD
SAR
DAC
Figure 4. Successive-approximations architecture.
Design Considerations and Implications
: A SAR converter can use a
single comparator to realize a high resolution ADC. But it requires
n
comparison cycles to achieve 
n
-bit resolution, compared to 
p
cycles for a pipelined converter and 1 cycle for a flash converter.
Since a successive-approximations converter uses a fairly simple
architecture employing a single SAR, comparator, and DAC, and
the conversion is not complete until all weights have been tested,
only one conversion is processed during 
n
comparison cycles. For
this reason, SAR converters are more often used at lower speeds
in higher-resolution applications. SAR converters are also well
suited for applications that have non-periodic inputs, since
conversions can be started at will. This feature makes the SAR
architecture ideal for converting a series of time-independent
signals. A single SAR converter and an input multiplexer are
typically less expensive to implement than several sigma-delta
converters. With dither noise present, SAR and pipelined converters
can use averaging to increase the effective resolution of the
converter: for every doubling of sample rate, the effective resolution
improves by 3 dB or 1/2 bit.
One consideration when using a SAR or pipelined converter is
aliasing
. The process of sampling a signal leads to aliasing—the
frequency-domain reflection of signals about the sampling
frequency. In most applications, aliasing is an unwanted effect that
requires a low-pass anti-alias filter ahead of the ADC to remove
high-frequency noise components, which would be aliased into
the passband. However, 
undersampling
can put aliasing to good
use, most often in communications applications, to convert a high-
frequency signal to a lower frequency. Undersampling is effective
as long as the total bandwidth of a signal meets the Nyquist
criterion (less than one-half the sampling rate), and the converter
has sufficient acquisition and signal sampling performance at the
higher frequencies where the signal resides. While fast SAR
converters are capable of undersampling, the faster pipelined
converters tend to be more effective at it. For more about
undersampling and dither, see http://www.analog.com/support/
standard_linear/seminar_material/practical_design_techniques/
Section5.pdf .
SIGMA-DELTA
The sigma-delta architecture takes a fundamentally different
approach than those outlined above. In its most basic form, a sigma-
delta converter consists of an integrator, a comparator, and a single-
bit DAC, as shown in Figure 5. The output of the DAC is subtracted
from the input signal. The resulting signal is then integrated, and

Analog Dialogue 33-8 (1999)
3
the integrator output voltage is converted to a single-bit digital
output (1 or 0) by the comparator. The resulting bit becomes the
input to the DAC, and the DAC’s output is subtracted from the
ADC input signal, etc. This closed-loop process is carried out at a
very high “oversampled” rate. The digital data coming from the
ADC is a stream of “ones” and “zeros,” and the value of the signal
is proportional to the density of digital “ones” coming from the
comparator. This bit stream data is then digitally filtered and
decimated to result in a binary-format output. For more about
sigma-delta conversion, see http://www.analog.com/support/
standard_linear/seminar_material/practical_design_techniques/
Section3.pdf.

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