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Analog Dialogue 33-8 (1999)Bog'liq analog-to-digital-converter-architectures-and-choicesADC/
COMPARATOR
DAC
D
A
⌺
⌺
+
–
+
+
D
SAMPLE
AND HOLD
A
D
A
Figure 3. A single pipelined converter stage.
Design Considerations and Implications
: Pipelined converters achieve
higher resolutions than flash converters containing a similar
number of comparators. This comes at the price of increasing the
total conversion time from one cycle to
p
cycles. But since each
stage samples and holds its input,
p
conversions can be underway
simultaneously. The total throughput can therefore be equal to
the throughput of a flash converter, i.e., one conversion per cycle.
The difference is that for the pipelined converter, we have now
introduced
latency
equal to
p
cycles. Another limitation of the
pipelined architecture is that the conversion process generally
requires a clock with a fixed period. Converting rapidly varying
non-periodic signals on a traditional pipelined converter can be
difficult because the pipeline typically runs at a periodic rate.
SUCCESSIVE APPROXIMATIONS
The successive-approximations architecture can be thought of as
being orthogonal to the flash architecture. While a flash converter
uses many comparators to convert in a single cycle; a SAR
converter, shown in Figure 4, conceptually uses a single comparator
over many cycles to make its conversion. The SAR converter works
like an old-fashioned balance scale. On one side of the scale, we
place the sampled unknown quantity. On the other side, we place
a weight (generated by the SAR and DAC) that has the value of 1/
2 of full-scale and compare the two values. This first weight
represents the most significant bit (MSB). If the unknown quantity
is larger, the 1/2-scale weight is retained; if the unknown quantity
is smaller, it is removed. This series of steps is repeated
n
times,
using successively smaller weights in binary progression (e.g., 1/4,
1/8, 1/16, 1/32, . . . 1/2
n
of full scale) until the desired resolution,
n
, is attained. Each weight represents a binary bit, with the largest
representing the most significant bit, and the smallest representing
the least significant bit.
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