2
Analog Dialogue 33-8 (1999)
PIPELINED
ARCHITECTURE
The
pipelined
(or pipelined-flash) architecture effectively overcomes
the limitations of the flash architecture. A pipelined converter
divides the conversion task into several consecutive stages. Each
of these stages, as shown in Figure 3, consists
of a sample-and-
hold circuit, an
m
-bit ADC (e.g., a flash converter), and an
m
-bit
D/A converter (DAC). First the sample and hold circuit of the
first stage acquires the signal. The
m
-bit flash converter then
converts the sampled signal to digital data. The conversion result
forms the most significant bits of the digital output. This same
digital
output is fed into an
m
-bit digital-to-analog converter, and
its output is subtracted from the original sampled signal. The
residual analog signal is then amplified and sent on to the next
stage in the pipeline to be sampled and converted as it was in the
first stage. This process is repeated through
as many stages as are
necessary to achieve the desired resolution. In principle, a pipelined
converter with
p
pipeline stages, each with an
m
-bit
flash converter,
can produce a high-speed ADC with a resolution of
n
=
p
×
m
bits
using
p
×
(2
m
–1) comparators. For example, a 2-stage pipelined
converter with 8-bit resolution requires 30 comparators, and a 4-
stage 16-bit ADC requires only 60 comparators. In
practice,
however, a few additional bits are generated to provide for error
correction. For more about pipelined ADCs, See http://
www.analog.com/support/standard_linear/seminar_material/
practical_design_techniques/Section4.pdf.
