| *EFI Note: Section 5.0 of the CIP BIOS Boot 1.01 defines the implementation for dual asynchronous channels. Note that this particular issue is also relevant for EFI systems, and designers of these systems will also use this specification for clarification of this particular implementation issue even though the rest of this specification is superseded by EFI.
Dual-channel controllers that require special software to serialize channel I/O for a single prefetch FIFO do not meet these requirements. Such designs require serial access to one of four devices, defeating the primary advantage of asynchronous dual-channel controllers. Furthermore, such devices are non-standard and require custom driver support.
B10.2.4.6 Controller and peripheral connections include Pin 1 cable designation with keyed and shrouded connectors
One edge of the keyed ribbon cable and the keyed connector of the ATA or ATAPI controller and peripheral device must indicate the Pin 1 cable orientation. Designation of the keyed connector must be clearly indicated on or near the connector.
B10.2.4.7 Controllers and peripherals comply with ATA/ATAPI-5 (or later)
All ATA/ATAPI controllers must meet the hardware and software design requirements listed in the AT Attachment with Packet Interface – 5 (ATA/ATAPI-5) standard (or later).
The ATA/ATAPI-5 (or later) standard defines hardware and software design requirements for ATAPI devices. ATA drives must comply with ATA-5, which defines the programming register set for PCI ATA bus master DMA, to ensure fully featured hardware and Windows-compatible device driver support.
ATAPI devices must respond to the DEVICE RESET command as defined in the ATA/ATAPI-5 standard (or later), regardless of their internal state. The controller can be reset when the computer is turned on (requests cleared, signature present), but any nondefault mode values must be left in their current state with the device driver (DRV) bit unchanged.
Devices such as hard disk drives that do not implement the PACKET command feature set must not implement the DEVICE RESET command.
ATA drives must implement the ATA STANDBY command, as defined in the ATA/ATAPI-5 standard (or later). Information on system power states and transitions can be found in Storage Device Class Power Management Reference Specification, Version 1.0.
B10.2.4.10 To tolerate Ultra DMA, ATAPI devices support the termination scheme defined in ATA/ATAPI-5 (or later)
See B10.2.4.4; B10.1.4.6
|
