• Implementation Of Page Tables In IA-32 Architecture
  • Linux: This Book Includes 4 Manuscripts. The Underground Bible to the unix operating System with Tools On Security and Kali Hacking to Understand Computer Programming, Data Science and Command Line




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    Linux This Book Includes 4 Manuscripts The Underground Bible

    Multi-Level Page Tables
    To address the logical address space of a large volume with a single page
    table, it has to be very large. For example, in an IA-32 architecture with a
    standard page size of 4 KB (addressing inside such a page requires 12 bits)
    the index in the table remains 20 bits, which corresponds to a page table of
    1 million elements.
    To avoid such large spreadsheets, the technology of tiered page tables is
    proposed. Page tables themselves are broken down into pages whose
    information is stored in top-level page tables. The number of levels rarely
    exceeds 2, but can reach 4.
    When there are two levels of tables, the logical address is broken down into
    an index in the top-level table, an index in the lower-level table, and offset.
    This technology has two main advantages. First, page tables are smaller in
    size, so they can be searched faster. Second, not all page tables should be in
    memory at a specific point in time. For example, if the process does not use
    some memory block, then the contents of all the lower-level pages of an
    unused block may be temporarily stored on the disk .


    Implementation Of Page Tables In IA-32
    Architecture
    The IA-32 architecture utilizes a two-tier page organization, starting with
    the Intel 80386. A table-top level called directory pages for each task
    should be given a separate directory page, a physical address that is stored
    in a special control register and where it automatically loads the hardware
    when switching context. Table bottom level is called a page table .
    The linear address is divided into three fields:

    Directory ( Directory ) - defines the directory entry pages,
    indicating the desired page table
    ❖ 
    Table ( Table ) -vyznachaye page table element that indicates the
    desired frame memory
    ❖ 
    Offset ( Offset ) - determines the offset within the frame, combined
    with the address of the frame forms a physical address
    The size of the directory and table fields is 10 bits, giving page tables
    containing 1024 elements, the size of the offset field is 12 bits, giving pages
    and frames 4 KB in size. One lower-level page table addresses 4 MB of
    memory (1 MB of frames) and the entire directory of pages has 4 GB .
    The page table elements at all levels have the same structure. Here are the
    following element fields:
    ❖ 
    Flag presence  ( Present ), equal to one of the page is in physical
    memory (it corresponds to the frame); equality of this flag means that
    the page is not in physical memory, and the operating system may use
    other element fields for its purposes
    ❖ 
    The 20 most significant bits  that set the frame start address to be
    multiple of 4 KB (1 MB of different start addresses can be specified)
    ❖ 
    Flag Access ( Accessed ), which is equal to one pin each time the
    reference device support paged to the corresponding frame


    ❖ 
    Flag Changes ( Dirty ), which confer equal to one while recording
    each transaction in the corresponding frame
    ❖ 
    Flag read-write ( Read / Write ), which specifies the rights to
    access the page or page table (for reading and write or read-only)
    ❖ 
    The privilege  ( User / Supervisor ) check box that specifies the
    processor mode required to access the page. If this checkbox is zero,
    the page can only be addressed from privileged mode, if units are also
    available from user mode
    Presence, access, and change checkboxes can be used by the OS to organize
    virtual memory .

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