Mobile PC Note: In mobile systems, the BIOS can configure the I/O system to share PCI interrupts.
B2.5.5 PCI Controllers/Devices - FAQs B2.5.5.1 Current PCI-related FAQs
See http://www.microsoft.com/winlogo/hardware/pci/.
B2.5.5.2 DAC requirement [Clarification ]
[SDG3:30-32]
Requirements for PCI adapters to support the PCI DAC command are defined in A1.1.6. See "Large Memory Enabled Device Driver Hardware and Software Requirements" in the Windows DDK. Design guidelines are summarized at http://www.microsoft.com/hwdev/newPC/PAEdrv.htm.
B2.5.5.3 AMR/MR PCI IDs [Clarification]
[PCI-0126]
AMR devices and MR devices on the system board are not exempt from the requirement for SID and SVID.
May 28, 1999
B2.5.5.4 Control Method for PCI IDs [Logo Program Clarification]
[PCI-0126; SDG3:30, 31]
PC 99 System Design Guide erroneously cited _PS0 as the control method to use. However, _PS0 moves a device from Dx to D0. (The parent PCI bus is at issue in this case; thus, it is actually Bx to B0.) The problem is that a bus must be powered on before it can be assigned a bus number. Therefore, _PS0 must be run before a bus number is guaranteed to exist. However, if power hasn’t been cut to the bus, or if the bus has not been reset, there will be a bus number remaining from before the bus was placed in the Bx state. This is why _PS0 seems to work in some systems. _REG runs immediately after Windows assigns the bus number and immediately before the PCI driver scans the bus for children. That is what makes _REG the appropriate vehicle for making the children coherent.
After the operating system has control of the system, the SVID and SID registers must not be directly writable—that is, implementations that write these registers before the operating system takes control must disable writing to the SVID and SID registers after the registers have been set and before Windows assumes control of the system. For details, see http://www.microsoft.com/hwdev/devdes/pciids.htm.
FAQ Date: August 26,1999
B2.5.5.5 PCI-PM 1.1 and PME# [Logo Program Clarification9]
[PCI-0130; PCI-0131; SDG3:50]
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