TI has a number of homogeneous and heterogeneous
multi- core DSP platforms, all of which are based on the hierarchal-in- terconnect architecture. One of the latest platforms is the TNETV3020 (Figure 5), which is optimized for high-performance voice and video applications in wireless communications infra- structure [8]. The platform contains six TMS320C64x1 DSP cores each capable of running at 500 MHz and consumes 3.8 W of power. TI also has a number of other homogeneous multicore DSPs, such as the TMS320TCI6488, which has three 1 GHz C64x1 cores and the older TNETV3010, which contains six TMS320C55x cores, as well as the TMS320VC5420/21/41 DSP platforms with dual and quad TMS320VC54x DSP cores.
Freescale’s multicore DSP devices are based on the StarCore 140, 3400, and 3850 DSP subsystems that are included in the MSC8112 (two SC140 DSP cores), MSC8144E (four SC3400
DSP cores), and its latest MSC8156 DSP chip (Figure 6), which contains six SC3850 DSP cores targeted for 3G-long-term evo- lution (LTE), WiMAX, 3GPP/3GPP2 and time division synchro- nous code division multiple access (TD-SCDMA) applications [9]. The device is based on a homogeneous hierarchical inter- connect architecture with chip level arbitration and switching system (CLASS).
PicoChip manufactures high-performance multicore DSP devices that are based on both heterogeneous (PC205) and homogeneous (PC203) mesh interconnect architectures. The PC205 (Figure 7) was taken as an
example of these multicore
DSPs [10]. The two building blocks of the PC205 device are an ARM926EJ-S microprocessor and the picoArray. The picoArray consists of 248 VLIW DSP processors connected together in a 2-D array as shown in Figure 8. Each processor has dedicated instruction and data memory as well as access to on-chip and external memory. The ARM926EJ-S used for control functions is a 32-b RISC processor. Some of the PC205 applications are in high-speed wireless data communi- cation standards for metropolitan area networks (WiMAX) and cellular networks [high-speed downlink packet access (HSDPA) and wideband code division multiple access (WCDMA)], as well as in the implementation of advanced wireless protocols.
Tilera manufactures the TILE64, TILEPro36, and TILEPro64 multicore DSP processors [11]. These are based on a highly scalable homogeneous mesh interconnect architecture.
The TILE64 family features 64 identical processor cores (tiles) interconnected using a mesh network of buses (Fig- ure 9). Each tile contains a processor, L1 and L2
cache memo- ry, and a nonblocking switch that connects each tile to the mesh. The tiles are organized in an 8 3 8 grid of identical gen- eral processor cores and the device contains 5 MB of on-chip cache. The operating frequencies of the chip range from 500– 866 MHz and its power consumption ranges from 15 to 22 W. Its main target applications are advanced networking,
digital video, and telecom.
SandBridge manufactures multicore heterogeneous DSP chips intended for software-defined radio applications. The SB3011 includes four DSPs each running at a minimum of 600 MHz at 0.9 V. It can execute up to 32 independent instruction streams while issuing vector operations for each stream using an SIMD datapath. An ARM926EJ-S processor with speeds up to 300 MHz implements all necessary I/O devices in a smart phone and runs Linux OS. The kernel has been designed to use the POSIX pthreads open standard [14] thus providing a cross-platform library compatible with a number of operating systems (Unix,
Linux, and Windows). The platform can be programmed in a number of high- level languages including C, C11, or Java [12], [13].
