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Protsessorda buyruqlarni bajarilish davri
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| bet | 4/10 | | Sana | 18.05.2024 | | Hajmi | 24 Kb. | | #242804 |
Bog'liq Protsessorda buyruqlarni bajarilish davri-fayllar.orgAccumulator
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AC
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16
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Processor register
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Instruction register
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IR
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16
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Holds instruction code
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Program counter
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PC
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12
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Holds address of the instruction
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Temporary register
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TR
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16
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Holds temporary data
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Input register
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INPR
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8
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Carries input character
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Output register
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OUTR
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8
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Carries output character
| Cont…
The following image shows the register and memory configuration for a basic computer.
11 0 11 0 15 0 15 0 15 0 7 0 7 0 15 0
Memory 4096 word 16 bits per word
| Cont….
The Memory unit has a capacity of 4096 words, and each word contains 16 bits.
The Data Register (DR) contains 16 bits which hold the operand read from the memory location.
The Memory Address Register (MAR) contains 12 bits which hold the address for the memory location.
The Program Counter (PC) also contains 12 bits which hold the address of the next instruction to be read from memory after the current instruction is executed.
The Accumulator (AC) register is a general purpose processing register.
The instruction read from memory is placed in the Instruction register (IR).
The Temporary Register (TR) is used for holding the temporary data during the processing.
The Input Registers (IR) holds the input characters given by the user.
The Output Registers (OR) holds the output after processing the input data.
Instruction Execution Cycle All computers have an instruction execution cycle. A basic instruction execution cycle can be broken down into the following steps:
Fetch cycle
Execute cycle
Although we have been concentrating on the CPU and memory, there are additional components in a computer such as the I/O modules which can interact with the processor. In an improved instruction execution cycle, we can introduce a third cycle known as the interrupt cycle. Figure 2 illustrates how the interrupt cycle fits into the overall cycle. Cont… Fetch cycle
To start off the fetch cycle, the address which is stored in the program counter (PC) is transferred to the memory address register (MAR). The CPU then transfers the instruction located at the address stored in the MAR to the memory buffer register (MBR) via the data lines connecting the CPU to memory. This transfer from memory to CPU is coordinated by the control unit (CU). To finish the cycle, the newly fetched instruction is transferred to the instruction register (IR) and unless told otherwise, the CU increments the PC to point to the next address location in memory.
Cont…. The illustrated fetch cycle above can be summarized by the following points:
PC => MAR
MAR => memory => MBR
MBR => IR
PC=PC+1
After the CPU has finished fetching an instruction, the CU checks the contents of the IR and determines which type of execution is to be carried out next. This process is known as the decoding phase. The instruction is now ready for the execution cycle. Execution cycle
Once an instruction has been loaded into the instruction register (IR), and the control unit (CU) has examined and decoded the fetched instruction and determined the required course of action to take, the execution cycle can commence. Unlike the fetch cycle and the interrupt cycle, both of which have a set instruction sequence, the execute cycle can comprise some complex operations (commonly called opcodes).
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