|
The actions within the execution cycle can be categorized into the following four groups
|
| bet | 5/10 | | Sana | 18.05.2024 | | Hajmi | 24 Kb. | | #242804 |
Bog'liq Protsessorda buyruqlarni bajarilish davri-fayllar.orgThe actions within the execution cycle can be categorized into the following four groups:
CPU - Memory: Data may be transferred from memory to the CPU or from the CPU to memory.
CPU - I/O: Data may be transferred from an I/O module to the CPU or from the CPU to an I/O module.
Data Processing: The CPU may perform some arithmetic or logic operation on data via the arithmetic-logic unit (ALU).
Control: An instruction may specify that the sequence of operation may be altered. For example, the program counter (PC) may be updated with a new memory address to reflect that the next instruction fetched, should be read from this new location.
For simplicity reasons, the following examples will deal with two operations that can occur. The [LOAD ACC, memory] and Conti…
[ADD ACC, memory], both of which could be classified as memory reference instructions. Instructions which can be executed without leaving the CPU are referred to as non-memory reference instructions.
LOAD ACC, memory
This operation loads the accumulator (ACC) with data that is stored in the memory location specified in the instruction. The operation starts off by transferring the address portion of the instruction from the IR to the memory address register (MAR). The CPU then transfers the instruction located at the address stored in the MAR to the memory buffer register (MBR) via the data lines connecting the CPU to memory. This transfer from memory to CPU is coordinated by the CU. To finish the cycle, the newly fetched data is transferred to the ACC. 1 The illustrated LOAD operation (Figure 4) can be summarized in the following points: 2 IR [address portion] => MAR 3 MAR => memory => MBR 4 MBR => ACC Cont.. ADD ACC, memory
This operation adds the data stored in the ACC with data that is stored in the memory location specified in the instruction using the ALU. The operation starts off by transferring the address portion of the instruction from the IR to the MAR. The CPU then transfers the instruction located at the address stored in the MAR to the MBR via the data lines connecting the CPU to memory. This transfer from memory to CPU is coordinated by the CU. Next, the ALU adds the data stored in the ACC and the MBR. To finish the cycle, the result of the addition operation is stored in the ACC for future use.
The illustrated ADD operation (Figure 5) can be summarised in the following points:
|
| |
