|
IR [address portion] => MAR 2 MAR => memory => MBR
|
| bet | 6/10 | | Sana | 18.05.2024 | | Hajmi | 24 Kb. | | #242804 |
Bog'liq Protsessorda buyruqlarni bajarilish davri-fayllar.org1 IR [address portion] => MAR 2 MAR => memory => MBR 3 MBR + ACC => ALU 4 ALU => ACC
After the execution cycle completes, if an interrupt is not dedect, the next instruction is fetched and the process starts all over again.
Interrupt Cycle
An interrupt can be described as a mechanism in which an I/O module etc., can break the normal sequential control of the central processing unit (CPU). Table 1 below, summarizes the most common form of interrupts that the CPU can receive.
The main advantage of using interrupts is that the processor can be engaged in executing other instructions while the I/O modules connected to the computer are engaged in other operations.
Cont.. |
Program
|
Generated by some condition that occurs as a results of an instruction execution, such as arithmetic overflow, division by zero, attempt to execute am illegal machine instruction, and reference outside a user's allowed memory space.
| |
Timer
|
Generated by a timer within the processor. This allows the operating system to perform certain functions on a regular basis.
| |
I/O
|
Generated by an I/O controller, to signal normal completion of an operation or to signal a variety of error conditions.
| |
Hardware failure
|
Generated by a failure such as power failure or memory parity error.
| Cont.. Up until now we have dealt with the instruction execution cycle on the hardware level. When interrupts are introduced, the CPU and the operating system driving the system, is responsible for the suspension of the program
currently being run, as well as restoring that program at the same point before the interrupt was detected. To handle this, an interrupt handler routine is executed. This interrupt handler is usually built into the operating system.
Before the interrupt handler routine can ran, several processes must occur first. A typical sequence of events is illustrated in Figure 6 below. After the completion of the interrupt handler routine, the normal sequencial fetch / execute cycle begins.
|
| |
