Figure  7-4: Convolution and stream processing diagram

 
76 
(7-2) 
))
(
(
)
(
t
x
f
t
y
ij
ij
In the Equation 7-2, the function 
)
(
x
f
is a nonlinear activation function defined in 
Equation 7-3. 
(7-3) 
1
1
2
1
)
(
x
x
x
f
We can model the solution of the Equation 7-1 on FPGA by implementing a simple 
approximation technique like the well-known digital differential analyzer (DDA). A DDA, 
also sometimes called “digital integrating computer”, is a digital implementation of the
differential analyzer. The integrators in DDA are implemented as accumulators, whereby 
the numeric results are converted back to a pulse rate by the overflow of the accumulator. 
The main advantage of the digital integrator, when compared to an analog integrator, is the 
scalable pre
cision. Also, in a digital integrator based on DDA, we don’t have drift errors and
noise due to the imperfection of electronic components. By accumulating over time of the 
values in a register, we can calculate the integral of input signals. The basic digital 
integrator is expressed by Equation 7-4. 
(7-4) 
S
K
X
X
n
n
1
In Equation 7-4, 
1
n
X
denotes the next state of the accumulator used for calculating the 
integral. The coefficient of 
K
is a constant factor that is less than 1; it is used for time-
scaling. In this equation, 
S
denotes the input signal for integration. We can map this 
technique on FPGA very easily by writing a behavioral code. After each rising clock pulse, 

 
77 
the equation updates the integral value. In this integrator, rounding or truncation errors 
are only due to the limitation of registers. Therefore, by increasing the register sizes we 
have a way to control/reduce this error. This error is cumulative. Thus, for low precision 
registers a lack of accuracy will be observed after a long time. The only way for overcoming 
to this problem is setting proper register sizes. 
By this way, we can compute directly the solution of differential equations. This 
simulation of analog computing is a fully parallel method for solving differential systems 
such as nonlinear equations and also to realize the integrator module within CNN. For 
integrator modules we must have access to the memory for storing the values and the cells 
output. The only critical term in CNN equation is the “Integrator”, which we
implement/realize through the DDA model. After approximating the basic CNN cell, we 
must cascade the cells together. All these steps are implemented in the CoDeveloper by 
using a Fixed-Point method. The result for each three rows will be stored in the memory. 
The CoDeveloper can handle the access to the external memory through the multi port 
memory controller (MPMC). This controller is a full feature memory controller that is 
compatible with standard DDR2 memory devices. This controller must be configured for at 
least one read and one write port. And for the many high-end video processing 
applications, there is no implicit limit on the number of read or writes ports in MPMC. 

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