Figure
7-2: Camera connection to the FMC board
Figure
7-3: Xilinx XtremeDSP Kit 3400
Figure 7-3 shows the Xilinx XtremeDSP kit which is very appropriate for image processing
and machine vision applications. This platform provides an embedded design framework
that can be customized with user defined video accelerators implemented in the FPGA
fabric. It has one Spartan FPGA with 3.4 million system gates and 126 DSP48 internal block
sets. This board has 256MB DDR2 and 256MB Compact Flash. The clock rate for the FPGA
is up to 200 MHZ.
LVDS
Deserializer
DS92LV1212A
Camera
Ref CLK
CLK
FMC Low
Pin count
Connector
FPGA
74
7.6
Electronic System Level and High Level Direct Convolution
Modeling
There are many possibilities to design a proper model for the video signal processing. As
main part of an Image processing engine, we need a convolution operator. This basic and
simple mathematic model is very useful for the implementation of many complex filters
such as first derivative and second derivative ones, finding edge operations, median filters,
noise cancelation, and etc. Due to the complexity of filters the best way to design a
convolution module in FPGA is using HDL programming. There are a lot of techniques to
implement and generate HDL code. One of the best techniques is using a high-end
technology of Electronic System Level design (ESL) like Impulse CoDeveloper. Impulse
CoDeveloper is a proper tool for developing custom IP modules such as convolution and
image processing modules. This tool allows designers to quickly develop custom filter
modules in standard c program. With this tool we can convert an untimed C program to
synchronized HDL code. One of the best facilities of this tool is the debugging module for
higher level C standard programs such as Microsoft visual studio and so on. CoDeveloper
results are fully compatible with standard C and VHDL. Almost all the data interactions
between modules and processes in CoDeveloper are based on stream passing and shared
memory. For creating these convolution modules we have designed two parallel C-
language processes named columns and convolution. The column process has access to the
incoming video stream and it can store the pixels values of 3 rows of an image in the
internal memory buffer for the convolution module. Figure 7-4 shows these two main
modules for splitting rows and convolution. The designer has access to the multi-channel
memory controller; by this way the program can use the pipelining technique. Depending
on the hardware platform we can use the pipelining technique in our design. Using the
Pipelining #Pragma switch, which is a pre-
compiled command in C, we can synthesize “for
-
loops” commands and the internal contents of that in a concurrent mode. If a system has
access to the dual-channel external memory, one can thereby synthesise some parts of the
code in a pipelining mode which has an interaction with external memory and registers
[122].
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