Figure
6-2: Rössler equation output graph that is generated after a solving by the analog
computing emulation on the FPGA board
68
Solving the Rössler equation for 6000 iterations in Matlab (time step size selected is 10^-9,
on a 3GHZ Dual Core CPU), takes 5400 ms, but in solving the same equation by hardware
through the emulated analog computing on FPGA with 300 MHz clock takes only 5
microseconds. The extremely high speed-up (compared to CPU) of many orders of
magnitude (more than several ten thousands) is evident. Figure 6-2 shows the XY plot of
Rössler equation output.
6.7.1
Future work
In the future, we are going to implement a system for generating the HDL code for solving
equations by a flow diagram. For modeling an ODE the future program will be node-based.
After coupling nodes by either code or a GUI, the program will be able to generate a gate
level HDL code for direct programming on FPGA. By this technique we can speed up the
design and implementation process of analog computing solvers on FPGA, which will be
capable of solving complex ODE equations and simulating complex systems in real time on
FPGA.
6.8
Concluding remarks
Each 18-bit integrator takes 1% of the FPGA resources, and each multiplier takes 2%
resource. In Xilinx Virtex-5 family there is a powerful chip (XC5VSX240T), which does fit
very well to the requirements of our analog computing emulation. This chip has 1k DSP48
slices, what is quite good for implementing integrators and multiplexers. The FPGA
synthesis program can combine one integrator and one or two multipliers and adders in
each DSP48. By this way we can implement many integrators, adder and multiplier on a
single FPGA chip. The obtained results are very encouraging, a speed-up or more than a
million has been reached when compared to Matlab performance on a normal PC.
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