Figure 6-1: Flow diagram for modelling the Rössler Equation (see Equation (6-2)) in the analog computing scheme emulated on FPGA Depending on the accuracy needed either for a given system simulation or for ODE solving,
we can define a specific data type for modules and basic elements. For each basic element
such as subtraction, addition and multiplier we define a fix-point data type with proper
“integer” and “precision” ranges. Depending on the complexity of the equations, we can
extend the number of bits used for storing both the “integer” and “precision” values. The
Most Significant Bit (MSB) bit is for sign, and for subtraction we use the 2’s co
mplement
method. The key advantage of a fix-point data coding in this case is the processing time and
also the saving of FPGA resources. In a floating point representation alternative data
coding we should have to use complex modules and architectures and it would
need/require more resources on the FPGA when compared to the fix-point alternative. Still
now, there is no general purpose architecture for solving any type of ODE equations [115],
but we propose a method for designing a system and solving ODEs in a straight forward
process (flow diagram). The flow diagram is consisting of many basic elements that are
coupled together.
Figure 6-1 shows a flow diagram for solving the so-
called “Rössler equation” (see Equation
6-2). In this diagram, outputs are registers, and internal connections are bus wires. The
data bus width for connecting the components is the same in all parts of the diagram. We
63
use 33 bits for sign registers, sign wires and storing the values and integrators. All
components are synchronous and the system is operated by a common clock.
