6.5
The “Digital Differential Analyzer” method
A digital differential analyzer (DDA), also sometimes called “digital integrating computer”,
is a digital implementation of the differential analyzer. The integrators in DDA are
implemented as accumulators, whereby the numerical results are converted back to a
pulse rate by the overflow of the accumulator. The main advantage of the digital integrator,
when compared to an analog integrator, is the scalable precision. Also, in a digital
inte
grator based on DDA, we don’t have drift errors and noise
[116] due to the
imperfection of electronic components. By accumulation over time of values in a register
we can calculate the integral of signals. The basic digital integrator is expressed by
Equation 6-1.
(6-1)
𝑋
= 𝑋 + 𝐾. 𝑆
In Equation 6-1,
X
denotes the next state of the accumulator used for calculating the
integral. The coefficient
K
is a constant factor that is less than 1; it is used for time scaling.
In this equation
S
denotes the input signal for integration. We can map this technique on
FPGA very easily by writing a behavioral code. After each rising clock pulse, the equation
updates the integral value. In this integrator, rounding or truncation errors are only due to
the limitation of registers. Therefore, by increasing the register sizes we have a way to
control/reduce this error. This error is cumulative. Thus, for low precision registers a lack
of accuracy will be observed after long time. The only way to overcoming to this problem is
setting proper register sizes.
64
6.6
Integration of hardware and software
The hardware implementation of systems for solving ODE equations by this DDA method is
one issue. Another issue is to ensure the communication of this module or system with the
physical world for setting parameters, coefficients, and initial conditions. For making a
System-on-chip (SoC) we need a central processor, a standard bus, and IO cores that are
integrated together. The IBM Processor Local Bus (PLB) is a technology that can support
and manage all of these facilities. PLBs are supported slave and master for controlling the
IP (Intellectual Property) on the bus. There is a possibility to passing the parameters and
values either through simple registers in PLB or by a first in first out method (FIFO) in PLB.
In Xilinx Virtex-4 family we can design a system based on PLB and custom IPs. In this case,
we integrated a PowerPC 405 (PPC) and Verilog modules as a custom IP by a 32bit PLB.
PPC is a hardcore 32bit processor that can provide good performance as a central
processor for controlling the custom IP and other peripherals. Through this bus also we
are able to send interrupt signals, so that Verilog modules can send a signal to PPC 405 as
an interrupt for doing some process on the output data. When the output of the module is
valid, it sends an interrupt signal through PLB to PPC 405. PLB and everything that is
connected to this bus is synchronous due to a common clock. By using System ACE
(Advanced Configuration Environment) CF (Compact Flash cards) technology we can
record results data in files. Then transferring or sending these data files to a computer (PC)
through either the normal or high speed serial link is then feasible. On the PC the results
will be visualized, saved or used for other purposes. In some Xilinx family there is a
possibility of using a softcore CPU like MicroBlaze, instead of a hardware-core (PPC405). It
is obvious that for using software-core CPU like MicroBlaze we need more logic slice
resources. Therefore, for saving logic slice resources in software integration, we applied a
hardware-core CPU (PPC 405).
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