Ultra fast cnn based Hardware Computing Platform Concepts for adas visual Sensors and Evolutionary Mobile Robots

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Alireza Fasih

6.7

Experimental results
For checking the accuracy of the developed system, we have implemented a Rössler
equation. Equation 6-2 shows this Rössler equation, which is a set of three highly non-
linear ordinary differential equations. This system can, depending on the set of parameters,
generate chaotic signals at the output. Equation 6-3 shows the set of parameters we have
used for generating chaotic waves. Traditional methods for solving the Rössler equation in
digital computers are based on numerical methods, such as Euler or Runge-kutta
algorithms. Depending on the initial conditions and the set of parameters, the system can
converge to specific orbits, to a point or diverge to infinity. For modeling this equation by
HDL we needed 6 multipliers, 3 integrators, and 4 adders. For realizing subtractions, we do
apply additions by the 2’s complement method. For coupling these components, we have to
use wire bus connections. Also, for storing the values of the states we need registers. There
is no exact rule for the definition/fixation of the number of bits for both integer and
precision parts of the fix-point data coding. Depending on the complexity of the system at
hand we can define a safe range for sign register and wires. For Rössler we have set in this
work a 33bit bus for connections between modules and accumulating the values in
integrators. Further, we have respectively set 1 bit for sign, 8 bit for the integer and 24 bit
for the fraction parts. With this setting for the variables and connections, the solutions of
the Rössler equation (x, y and z) will be limited within maximum range of ±255 (1-bit sign,
8-bit integer and 24-bit fraction). We have implemented this equation on a Xilinx ML405
evaluation board with a 100Mhz clock rate. This board is based on Virtex-4 FX20 family,
with 20k logic cells and 32 DSP48 slices.
(6-2)
𝑑𝑥
𝑑𝑡
= −𝑦 − 𝑧
𝑑𝑦
𝑑𝑡
= 𝑥 + 𝑎𝑦
𝑑𝑧
𝑑𝑡
= 𝑏 + 𝑧(𝑥 − 𝑐)

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(6-3)
a = 0.41
b = 1.15
c = 4.16
At its most basic level, a DSP48 is a multiplier with a combination of adders and many
optional operations. It has an 18-bit sign input signal and a 36-bit sign output result. This
result is then sign extended to 48-bits, it can either be fed into the adder or connected
directly to the output of a DSP48. Pipeline registers are a unique advantage of the DSP48
block compared to other FPGA DSP architectures [7]. Xilinx has dedicated many DSP48
slice in Virtex-4 and Virtex-5 family for speeding-up of calculations. The amount of
resources used after synthesis for solving the Rössler equation in terms of DSP48 slices,
Flip-Flop slices and 4-Input LUT Slices is shown in the Table 6-1.
Table 6-1: FPGA Resources used for Implementation of an Emulated Analog
Computing Solver of the Rössler Equation on FPGA
Integrated Software Environment
(ISE) is the Xilinx® design software suite that allows you
to take your design from design entry through Xilinx device programming. By disabling the
DSP48 slices in this program, the system tries to synthesize the code and design by normal
logic slices. The FPGA synthesis report is in Table 6-2. For the 2 scenarios with and
without DSP48 slices; the Table 6-2 shows what difference there is in terms of FPGA
resources use/consumption between the two alternatives.

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Table 6-2: Benchmarking of resources used for FPGA synthesis report for implementing a 33-bit ODE solver of
the Rössler Equation
In some Xilinx family FPGA, there is no DSP48 slice for implementing integrators,
multipliers and basic elements. Thus we need more logic cells to implementing these
resources. According to Table 6-2, 62% DSP48 (20 slice DSP48 in Virtex-4, FX20 FPGA) is
equal to 21% (3600 slice, 4-bit LUTs in Virtex-4 FX20 FPGA) of basic logic slices.

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