66
(6-3)
a = 0.41
b = 1.15
c = 4.16
At its most basic level, a DSP48 is a multiplier with a combination of
adders and many
optional operations. It has an 18-bit sign input signal and a 36-bit sign output result. This
result is then sign extended to 48-bits, it can either be fed into the adder or connected
directly to the output of a DSP48. Pipeline registers are a unique advantage of the DSP48
block compared to other FPGA DSP architectures [7]. Xilinx has dedicated many DSP48
slice in Virtex-4 and Virtex-5 family for speeding-up of calculations.
The amount of
resources used after synthesis for solving the Rössler equation in terms of DSP48 slices,
Flip-Flop slices and 4-Input LUT Slices is shown in the Table 6-1.
Table 6-1: FPGA Resources used for Implementation of an Emulated Analog
Computing Solver of the Rössler Equation on FPGA
Integrated Software Environment
(ISE) is the Xilinx® design software suite that allows you
to take your design from design entry through Xilinx device programming. By disabling the
DSP48 slices in this program, the system tries to synthesize the code and design by normal
logic slices. The FPGA synthesis report is in Table 6-2. For the 2 scenarios with and
without DSP48 slices; the Table 6-2 shows what difference
there is in terms of FPGA
resources use/consumption between the two alternatives.
67
Table 6-2: Benchmarking of resources used for FPGA synthesis report for implementing a 33-bit ODE solver of
the Rössler Equation
In some Xilinx family FPGA, there is no DSP48 slice
for implementing integrators,
multipliers and basic elements. Thus we need more logic cells to implementing these
resources. According to Table 6-2, 62% DSP48 (20 slice DSP48 in Virtex-4, FX20 FPGA) is
equal to 21% (3600 slice, 4-bit LUTs in Virtex-4 FX20 FPGA) of basic logic slices.
