Ultra fast cnn based Hardware Computing Platform Concepts for adas visual Sensors and Evolutionary Mobile Robots

 
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standard designed to provide very high visual quality on digital video processing and 
displaying systems. 
Figure 
7-1: General architecture for stream processing 
Digital DVI signals are partially compatible with 
High Definition Multimedia Interface
(HDMI) signals. In this case, we have used an FMC video grabber daughter board as a 
capturing unit. This board has a central pico-processor to control both the signals and the 
synchronization with the FPGA board. The video stored in the buffer does contain the pixel 
values. After video the capturing phase, we must extract and split rows for the video 
processing module. The video processing module has access to the video memory for 
storing and retrieving video signals. The main property/function in the video processing is 
a convolution based filter. Depending on the convolution size, we must split the video 
stream into many rows and keep it in the internal FPGA memory. 
7.5
 
Hardware Platform Specification 
In the implementation of this work, we do use a platform comprising the Xilinx XtreamDSP 
3400 and a Video FMC daughter board which has a Pico Microblaze for video signals 
capturing. It has a DVI input, a composite/S-video input and output, and a camera input. 
This board has two camera interfaces to allow the capturing of data from two cameras at 
the same time and simultaneously. The camera we use is a custom CMOS camera based on 
the Micron MT9V022 image sensor chip. This camera sends a high-speed LVDS (Low-
Voltage Differential Voltage) data stream format to the board. It operates with a 26.6 MHZ 
VGA 
Frame Buffer 
IP 
PPC/CPU 
Memory 
DVI IN 

 
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clock rate that is generated by a reference clock which is provided via a fixed-frequency 27 
MHZ oscillator on the board. Figure 7-2, shows the camera connection diagram to/in the 
FMC board. In the initial step we must define the voltage source level for the FMC board as 
well. 

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